Hello. Finally, I had a chance to check ADC gates for many detectors. I put the postscript files in the "http://pii3.brahms.bnl.gov/~hito/run2001/timing" directory. Also, the setting for checking signal is shown in Timing_Setting.eps file. Therefor, if you are the person responsible for those detectors, please check them. However, here is the summary. 1. Tile --- Tile gate has been moved since gate was chopping signal. 2. H1 --- Looks fine. 3. H2 --- Looks fine. 4. BB --- Looks fine. 5. TOFW --- Looks fine. 6. RICH --- Gate is too late. Maybe??? (It seems that there is no easy way to gain more time.???) (Or, maybe the early signal is a junk signal so it is ok???) 7. Si --- Of couse it is fine. I did not show the plot since I am the responsible for that one. 8. C1 --- Since Ramiro just checked that gate and moved it, I did not include the plot. 9. ZDC --- Since Michael is here (BNL), I suppose he will check it. Did I miss any other detectors??? hiro
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