PowerPoint Presentation

Frank L. H. Wolfs

Department of Physics and Astronomy, University of Rochester

Universal Logic Module:
Programming Status

ĄFPGA Firmware:

ĄProgrammable delay on all inputs, 25É400 ns.

ĄPre scaling on all NIM outputs by 1É255.

ĄPulse area and baseline determined for every pulse.

ĄProgrammable upper & lower threshold on all ADC inputs.

ĄEither self-triggered or externally triggered.

ĄComplete 12 microsecond history of inputs, outputs, and ADC.

ĄPHOBOS trigger firmware.

ĄOne VHDL module implements PHOBOS-specific Ňlogic equationsÓ.

ĄA few pages of well commented VHDL code.

ĄWill need to be customized Ňas neededÓ.

ĄEmbedded micro processor:

ĄStill below the limit of the free Keil compiler (90% of the 4kB limit).

Ą Communication with FPGA implemented.

Ą Setting the ADC gain and input offset implemented.

Ą USB command protocol implemented.

Ą Histogramming and board monitoring needs the full compiler.