PowerPoint Presentation

Frank L. H. Wolfs

Department of Physics and Astronomy, University of Rochester

Universal Logic Module:
Programming Status

•FPGA Firmware:

•Programmable delay on all inputs, 25…400 ns.

•Pre scaling on all NIM outputs by 1…255.

•Pulse area and baseline determined for every pulse.

•Programmable upper & lower threshold on all ADC inputs.

•Either self-triggered or externally triggered.

•Complete 12 microsecond history of inputs, outputs, and ADC.

•PHOBOS trigger firmware.

•One VHDL module implements PHOBOS-specific “logic equations”.

•A few pages of well commented VHDL code.

•Will need to be customized “as needed”.

•Embedded micro processor:

•Still below the limit of the free Keil compiler (90% of the 4kB limit).

• Communication with FPGA implemented.

• Setting the ADC gain and input offset implemented.

• USB command protocol implemented.

• Histogramming and board monitoring needs the full compiler.