(H.P. 8/1998)

The first 6 chips of the PHOBOS VA64HDR1 production run were tested. Before delivery the chips have been evaluated by IDE.

6 chips out of a batch of 94 chips were mounted on a MS3L hybrid (0006-string 0). The chips were operated at our standard settings of

Vfp=-350mV

Vfs=+700mV

Ipre=3000uA

Isha=100uA (nominally 68uA but limited by the repeater)

Ibuf=140uA

1. The switch-off point of Vfp was measured to be approximately –390mV
2. The signal peaking time at this settings is 1.2us
3. Gain measurement:

The gain was determined as the slope of output signal versus input charge in a range of 0 to 120fC input. The average chip gain varies from 6.2 to 6.8 mV/fC, i.e. about 10%

The gain variation within one chip is on average +-2%. The maximal variation in this chip sample is +-3% (2^nd chip). The IDE specification is 2.5%.

4.) Pedestal:

The channel pedestal varies by about 350mV within the chip. Using an average gain of 6.4mV/fC this corresponds to a pedestal variation of 15 MIPs. The average chips pedestal varies by about 100mV.

5.) Linearity

To determine the linearity the output amplitude is averaged over channel 2 to 63 at a given input signal. The plot shows the response for all 6 chips individually

Note: The chips are order in the plot’s legend as mounted on the hybrid (chip 0 to chip5)

6.) Noise measurement:

The noise was measured using source test setup with a random trigger. The common-mode-correction was enabled during the test. No detector is connected to the chips.

The average rms noise is 1.00mV ,i.e. about 970 electrons.