A / C ||||LEVEL COMMAND / HIGH LEVEL SET ACQUISITION MODE AND LOW LEVEL CAUSE CONVERTING MODE

A / S ||||LEVEL COMMAND / HIGH LEVEL SETS ASYNCHRON AND LOW LEVEL SETS SYNCHRON MODE FOR DATA READOUT

A ||||LEVEL SIGNAL / HIGH LEVEL DEFINING VALID SIGNAL INFORMATION IN THIS MARKED CHANNEL

ALLCRD ||||STATUS SIGNAL / ALL CHANNELS ARE READ FROM ONE POINTED CHIP

AOUT[5:0] ||||DATA / CHANNEL ADDRESS PASSED OUT INTO FRONT END ELECTRONICS SYSTEM BUS

AQ ||||LEVEL SIGNAL / HIGH LEVEL CAUSE START OF ACQUISITION MODE

AQWE ||||LEVEL SIGNAL / HIGH LEVEL CAUSE WRITE ENABLING INTO POINTED SCAM CELL

BT[3:0] ||||FOUR BITS CHIP INTERNAL SCAM CELL POINTER WHICH IS ISSUED BY PTR UNIT

BXC ||||CLOCK DERIVED FROM 2BXC

BXT[3:0] ||||FOUR BITS SCAM CELL LOCATION FOR WHOLE SYSTEM REQUESTED BY FRONT END CONTROLLER

CHADR[5:0] ||||SIX BITS CHANNEL ADDRESS CREATED IN CHADR UNIT

CNVDN ||||LEVEL SIGNAL / HIGH LEVEL DEFINE CONVERSION DONE STATUS

CNVRT ||||COMMAND / EACH TRANSITON FROM LOW INTO HIGH LEVEL START NEW CONVERSION IF OLD ONE IS DONE

CONV ||||LEVEL SIGNAL / HIGH LEVEL ENABLE COMPARISON MODE FOR VOLTAGE COMPARATOR

CONVDN ||||STATUS SIGNAL / HIGH LEVEL DEFINE END OF CONVERSION

CS[3:0] ||||FOUR BITS SIGNAL FOR CHIP SELECTION

D[5:0] ||||DATA VECTOR FROM COUNTER FOR CONVERT COMMAND CREATOR

DATA[6:0] ||||DATA VECTOR FROM SEVEN BITS CONVERSION COUNTER

DB[5:0] ||||COMPLEMENTARY DATA VECTOR FROM COUNTER FOR CONVERT COMMAND CREATOR

DO ||||LEVEL SIGNAL FROM CONVERTING COMPARATOR (ALSO DO[7:0] VECTOR)

DOUT[7:0] ||||DATA / CONVERSION DATA INFORMATION PASSED INTO FRONT END ELECTRONICS SYSTEM BUS

DT[7:0] ||||CHIP INTERNAL DATA BUS

EN ||||LEVEL SIGNAL / HIGH LEVEL ENABLING WRITING IN OR READING OUT FROM POINTED SCAM CELL

FIN ||||LEVEL SIGNAL / HIGH LEVEL ENABLING COMMUNICATION WITH POINTED CHIP ON GLOBAL LEVEL

Fl ||||LEVEL SIGNAL / HIGH LEVEL ENABLING COMMUNICATION WITH THIS SELECTED CHANNEL ON LOCAL LEVEL

FO ||||LEVEL SIGNAL / HIGH LEVEL INDICATE NO DATA OR RESETED READ DATA IN SELECTED CHANNEL

FOUT ||||LEVEL SIGNAL / HIGH LEVEL INDICATED NO DATA OR ALL DATA READ FROM POINTED CHIP

GA[3:0] ||||FOUR BIT VECTOR DEFINING GEOGRAPHIC CHIP ADDRESS

HRC ||||LEVEL SIGNAL / HIGH LEVEL DEFINING HIGH.RANGE OF CONVERSION (ALSO HRC[7:0] VECTOR)

INIT ||||LEVEL COMMAND / HIGH LEVEL INITIALIZING CHIP

MSYNC ||||POSITIVE EXTERNAL MASTER SYNCHRONIZING PULSE COMING FROM FRONT END CONTROLER

NEXT ||||POSITIVE PULS / INTERNAL CONTROL SIGNAL FOR RELEASING NEXT VALID DATA FROM POINTED CHIP

NEXTRQ ||||ONE SHUT LEVEL COMMAND / TRANSITION FROM LOW INTO HIGH LEVEL SET NEXT DATA FOR READING

PCNTR ||||EDGE SIGNAL / RISING EDGE INCREMENTING COUNTER FOR SCAM CELL POINTER

PMPEN ||||LEVEL SIGNAL / HIGH LEVEL ENABLING ACTION FOR CHARGE PUMP

RDONE ||||LEVEL SIGNAL / HIGH LEVEL RESETTING ALL SATU UNITS AND PREPARING FOR NEXT CONVERSION

RE ||||LEVEL SIGNAL / HIGH LEVEL ENABLES READING FROM POINTED SCAM CELL

READ ||||EDGE SIGNAL / RISING EDGE CAUSES READING FROM EXTERNAL BXT[3:0] CHANNEL INTO CHIP BXT UNIT

RESET ||||LEVEL SIGNAL / HIGH LEVEL RESETTING READING-WRITING SCAM BUFFER

RESET2 ||||LEVEL SIGNAL / HIGH LEVEL RESETTING CONVERTING BUFFERS

S/D ||||LEVEL COMMAND / HIGH LEVEL SETS SINGLE MODE AND LOW LEVEL SETS DOUBLE-CORRELATED MODE

SAMPLE ||||LEVEL SIGNAL / HIGH LEVEL SAMPLING COMPLEX VOLTAGE LEVELS INTO CONVERSION STAGE

SELRNG ||||LEVEL SIGNAL / HIGH LEVEL SELECTS EXTERNAL ANALOG VOLTAGE LEVEL REQUIRED FOR RANGE

SELTHR ||||LEVEL SIGNAL / HIGH LEVEL SELECTS EXTERNAL ANALOG VOLTAGE LEVEL REQUIRED FOR THRESHOLD

SRM ||||LEVEL COMMAND / HIGH LEVEL SETS READ MODE FOR POINTED CHIP

SYNC ||||LEVEL SIGNAL / HIGH LEVEL INDICATES SYNCHRONIZATION ERROR IN THE SYSTEM

SYNCER ||||STATUS SIGNAL / HIGH LEVEL INDICATES SYNCHRONIZATION ERROR IN THE SYSTEM

SYNCR ||||EDGE SIGNAL / RISING EDGE RESETTING SYNCHRONIZATION ERROR STATUS SIGNAL

TEST ||||LEVEL COMMAND / HIGH LEVEL SETS TEST MODE OF MEASUREMENT

WE ||||LEVEL SIGNAL / HIGH LEVEL SETS WRITE MODE INTO SCAM AND LOW LEVEL SETS READ MODE FROM SCAM

2BXC ||||EXTERNAL CLOCK

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