T0 Gating. 01/11/05

Run 16134. CuCu200MinBias

Scaler rates.

T0P1 signals taken from the lower patch panel

T0P1 signal and gate.

T0P1 signal and gate, persistent mode

New run 06:17:17 pm

T0P1

The same T0P1, averaged over 1000 events

TOF cable 045

Summary:

The gating is not bad, especially taking into account that on the signal is additionaly delayed between patch pannel and ADC. It is safe to move the gate left by 20 ns.

After modifications

The OR input of G11C (TOF ADC Gate) is taken from G5.11 (L0 from TML0.10) instead of G12.3 (L0 from TML0.2). The G12.3 probably overloaded. This way we could gain 10-14 ns.

T0P1

T0P1 averaged for 1000 events.

Troubled Run 16134s0

tt->Draw("ADC22[49]>>h1")

In this run the L0 (TDC08[38]) = 8420, rms 84.35

PR04 Run 13316s30 looks good

tt->Draw("ADC22[49]>>h1")

In this run the L0 = 1680, rms = 1.297

After modifications. Run 16142

tt->Draw("ADC22[49]>>h1"). Looks good.

t->Draw("ADC22[49]:TDC09[49]>>h2","","colz") for troubled run 16134

tt->Draw("ADC22[49]:TDC09[49]>>h2","","colz") for run 16142. Looks good now

The T0 ADC spectra now looks good. 10 ns makes the difference!