07/02/03

Schematic drawing of the PhTDC is ready.

Design of the PCB layout for PhTDC has started. It will take 1 month to finish.

07/14/03

Search for most critical components of the PhTDC is finished.

The maximum lead-time is 4 weeks.

07/28/03

Design of the PCB layout for PHTDC is finished. The picture is here.

07/30/03

Paperwork for obtaining visa for Sergei and Alexei have started.

07/31/03

• The PCB layout for PHTDC was checked by Andrei and has been approved for manufacturing.
• Got quotation from several PCB manufacturers. The delivery time is 5 – 10 days, the cost estimate was correct.
• Jorgen Christiansen (designer and producer of the HPTDC chips) said it is possible to deliver chips in 1-2 months. Bolek and Christof are helping to order 80 chips.
• All necessary files for PCB manufacturing are in hand.
• Meeting with Tom Ludlam (attended: Mark an Andrei). He supports the project and will talk to RHIC officials to find the funds for the project.

We are ready to place an order for PCB manufacturing.

08/01/03

Installed Xilinx ISE 5.2. Fortunately it supports our XCV300E chip and is free.

The Xilinx programming has started.

8/5/03

The first version of the FPGA design have been successfully synthesized and routed. Implemented are the VME interface and the memory. It constitutes about 75% of project resources and about 25% of the logic. The design occupies ~ 25% of the chip’s resources.

According to Jorgen Christiansen, the HPTDC chips are planned for testing at CERN on the first week of September, it will be ready for delivery on the second week of September.

8/6/03

The funding for PhTiMeS has been approved. We can prepare the POs using capital account.

The preliminary version of the FPGA design with correct pin assignment is finished. Files are, as usual, at http://www.bnl.gov/phobos/Detectors/DataAcquisition/PhTiMeS/phtdc/phtdcx.zip

8/27/03

The Conduant is experiencing problems with the delivery of the TK200.

First, the Linux drivers do not work on 2-processor motherboard. This problem is being solved.

Second and very important:

The StreamStor board does not support the DATA FIFO mode. The product is optimized for shuttle operation. They were developing the DATA FORKING mode to meet our needs but from my point of view this mode is useless for us. DATA FORKING: data are recorded at the full speed and also copied to the PCI port; since the PCI link is slower then recorder, the PCI stream is chopped.

After a brainstorming they suggested following:

They will introduce simultaneous recording and reading. Since the recorder’s bandwidth is 200 MB/s it is possible to write at 50 and read at 25 MB/s. The problem is that this mode requires positioning of the heads between reading and writing. They will submit a written proposal shortly.

They need at least 4 weeks to implement this mode. At the same time they can deliver the existing system for us to begin developing the rest of the system.

9/8/03

PO for PhTiMeS have been sent out to CEM Ltd. The estimated delivery time for 17 boards of PhTDC is October 1^st.

The HPTDC chips received from Jorgen Christiansen. Christof is arranging delivery to BNL.

Conduant informed that they can ship the TK200 this Thursday. The firmware could be ready by the end of September.

9/12/03

Successful dry run.

9/17/03 Summary status of the DAQ and PhTiMeS

DAQ

TK200 is scheduled for delivery on September 19.

The Conduant co got best engineers working on firmware upgrade (implementation of PWR mode)

PhTiMeS

The CEM Ltd estimates that assembled PHTDC boards will be delivered on October 1.

The schematic design of the logic module PhLoM is finished.