Trigger Readout Connection Table

Valid since 04/19/00. Prepared by Andrei Sukhanov.

A sketch of the L0/L1 logic can be found here.

Name Source module TDC
slot #		 Chan
nel #		 Virtual
detector		 Trig
bit		 Valid since Note
PN A1C 9 48 GX00 At least 1 hit in negative paddle counter. 3
PP A1D 9 49 GX01 At least 1 hit in positive paddle counter. 3
CC Blue C12B 9 50 GX02 Blue crossing clock
PNPP(n) wide A8C 9 51 GX03 6/02 Wide coincidence PN(n)*PP(n). Previously it was CC_delayed from B5B
PNPP wide A2C 9 52 GX04 L0.11 PN*PP coincidence
ZTrig D5A 9 53 GX05 L1.7 ZN ZP coincidence
L0 G11B 9 54 GX06 Slightly delayed L0.
L1 TML1O0 9 55 GX07 Generated by TML1 board.
ZN D4B 9 56 GX08 At least 1 hit in negative ZCal
ZP D4C 9 57 GX09 At least 1 hit in positive ZCal
PN(n) A9A 9 58 GX0A At least n hits in negative paddle counter
PP(n) A9B 9 59 GX0B At least n hits in positive paddle counter
CC Yellow C12C 9 60 GX0C Yellow crossing clock. applied 5/26/00, run 3120
PNPP(n) narrow A8B 9 61 GX0D 6/04 narrow coincidence
PNPP narrow A2B 9 62 GX0E 6/04 narrow coincidence
ADCGate G5C 9 63 GX0F

~G11B

 6/08

run 3777

 ADC6 Gate for Paddles

TOF Gate

Note 1

The Notation L0.11 means that this trigger goes to TML0 board input 11. It can be read back as bit 11 at L0 latch register using GetTrigL0Latch()&0x800

Note 2

On 05/23/00 at 1000 (run 3060 Paddle Cosmic) the delay cable for all trigger time signals (TDC09 channels 48:63) were changed from 150 ns  to 190 ns

Note 3

Before 05/23/00 at 1000 ((run 3060 Paddle Cosmic) the PN and PP signals were connected to A1A, A1B respectively.

 

Trigger Scalers Connection Table

The scaler is Caen Model V560N. This is 16 channel 32-bit scaler. It is cleared only on program restart. The scaler value can be obtained using TPhEventBufferInfo::GetScaler(index)

Scaler
Channel		 Name Source Valid
since		 Notes
0 ZP*ZN*CC narrow D4A 7/10/00 Before 7/10 it was connected to D2C
1 PN*PP wide A2C 5/1/00 wide range 38 ns
2 ZN D4B 5/1/00  
3 ZP D4C 5/1/00  
4 PN A1A 5/1/00  
5 PP A1B 5/1/00  
6 PN*PP narrow A2B 6/2/00 narrow coincidence
7 PNPP(n) narrow A8B 6/4 narrow coincidence
8 PNPP(n) wide A8C 6/15 wide coincidence. Between 6/14 and 6/15 it was mistakenly connected to A2B
9 ZP*ZN*CC wide D4B 7/10/00  
10        
11        
12        
13        
14        
15 CC C12B 6/6 Crossing clock.

 

Trigger bits

Trigger bits of the L0 board. Accessible using TPhEventBufferInfo::GetTrigL0Latch()

L0
bits		 Name Source Valid
since		 Notes
0 reserved      
1 reserved   run 3525  
2 reserved   run 3525  
3 reserved   run 3525  
4 reserved   run 3525  
5 reserved      
6 reserved      
7 reserved      
8 Heartbeat   06/05/00 Heartbeat generator T=8sec. Provides triggers in absence of the beam for Si monitoring.
9 TimeCal   01/01/00 Time calibrator. It is ON for plastic time calibration runs
10 Pedestal   run 3525 100 Hz generator, switched on for Si Pedestal Run
11 reserved   run 3525 before 06/14 it was PN*PP
12 PN*PP wide   run 3525 Our main trigger so far
13 reserved   run 4296 ZTrig
14 CC     Crossing clock
15 Veto     External signal to veto L0 board. Should never be seen.

 

Trigger bits of the L1 board. Accessible using TPhEventBufferInfo::GetTrigL1Latch()

L1
bits		 Name Source Valid
since		 Notes
0 L0 Output of the L0 board. Problem seeing this bit in the data: It is always 0.
1 PNPP narrow A2B run 3525 Before the run 3540 The CC was connected and coinc. level was 2
2 reserved
3 reserved
4 reserved
5 reserved
6 reserved run 3535

run 3540

 PNPP(n) wide A8C moved here from L1.1 (was there since 3525) due to problems in L1 board

Removed.
7 01/01/00
8 0
9 0
10 0
11 0
12 0
13 0
14 L1 Output signal.
15 Busy Generated inside the L1 board