During any running mode, the high voltage should be on and monitored. The person on shift is initially responsible for making sure there is no flaky behavior of the high voltage on any of the TOF PMT’s. The high voltage is controlled and monitored using the HV Slow Controls VI in Labview on the Plastic HV & Camac Slow Controls computer located on the console. The details on using this VI are located in the manual. A template has been generated which is located on this computer, and it holds all the requested voltages of each PMT in the TOF and in the trigger counters.

The discriminators in the tunnel have to be set to remote mode during any running mode. This is achieved by running the Camac Controls VI in Labview on the Plastic HV & Camac Controls computer in the console. The details on using the VI are located in the manual. All channels need to have to be unmasked and have a threshold of at least 25mV to cut out noise. The width should be set at 100ns. When the discriminators are in local mode, the thresholds are set to 500mV and the widths are approximately 110ns.

Once the high voltage and discriminators are set properly, there is nothing else to do. The discriminators most likely should be set to 500mV with a width of 100ns, and all the channels should be unmasked. These values are subject to change but are the most common mode of operation. The high voltage values should be in the range from +700 to +900V. Any disabled or tripped channels will be noted in the database, but an effort should be made to insure all channels are working properly.

There are a few changes to be made for a cosmic run as compared to a physics run. Neither the discriminators nor the high voltage need to be changed. The threshold for the trigger discriminator, which is located in slot 20 as seen on the front panel of the Camac controls VI, should be set at a proper level. A level of 75mV is the most common, since this specifies that at least two channels in either wall segment has to fire. At this level, the count rate should be approximately around 100 counts per second. A higher level can be used to look at cosmic shower events, since it requires more scintillators to be hit at once. On the other hand, if the threshold of the trigger discriminator is set to 25mV, the number of events with only one PMT anode firing can be found. This number in the past was found to be zero, but if it increases, they have to be considered in the analysis.

The 4-fold logic unit used in the TOF self-triggering system, which is located above the Fastbus crate, has to be set to a one coincidence level with channels A and B unmasked. Channels C and D need to be masked. The output has to be routed into the trigger electronics.

E. Checking ADC gate and TDC start for TOF and Time Zero.

1.  The gates can not be checked unless there is a trigger being supplied to the fastbus.  How the trigger is being generated needs to be understood before any checks can be done in order to understand the timing between the trigger and the signal. 

2. Locate the CAT module in the Fastbus.

3. Locate the ICA Stop and the ADC gate inputs on the CAT module.  (Note: Both inputs need to be properly terminated.  Both inputs for either the ADC gate or the ICA Stop  needs to be terminated with 50 ohms.)  The ICA Stop is the start for the TOF TDCs and the ADC gate is the gate for the ADCs.   The level zero trigger schematic illustrates the layout of the TOF TDC start and ADC gate.

4. The ADC signal will be measured from the patch panel below the fastbus.  It doesn't matter which channel is used, and ideally, a couple of channels from both wall should be checked.

5. The TDC stop is routed over the ribbon cable.  This cable needs to be rerouted into a ECL-NIM converter.  A converter is located in the NIM bin above the fastbus.

6. Grab two 8ns cables, or two cables of the same length.  Route one from the CAT module using the empty, or terminated, input for either the ICA stop or the ADC gate.  Route the other cable from the patch panel to measure the PMT signal with respect to the ADC gate, or route one cable from the ECL-NIM converter to measure the TDC stop with respect to the TDC start.

7a. For TDC timing:  The time difference to measure is the time between the leading edge of the start and the leading edge of the stop.

7b. For ADC timing:  The time difference to measure is the time between the leading edge of the ADC gate and the leading edge of the signal. (Collisions needed)

8. The time difference between the signal input to the TDC or ADC and the input to the CAT module is the value that needs to be measured.  This requires some arithmetic.  Given a cable from the CAT to the scope with a time of X ns, and the cable that measures the signal with a time of Yns.  DeltaT is the time from the leading edge of the gate (or start) to the leading edge of the signal (or stop) as measured on the scope.   

8a. Timing for the TOF TDCs:   The ECL-NIM converter  will delay the stop by 5ns as seen on the scope.  Correct time differnce = DeltaT + 5ns - Xns.

8b. Time for the Time Zero TDCs:  The ECL-NIM converter will delay the stop by 5ns as seen on the scope.  Note any ribbon cable not being measured.  The short ribbon cable that routes the two time zero ribbon cables into one is about 3ns long.  If this cable isn't routed to the ECL-NIM conveter, Correct time difference = DeltaT + 5ns - 3ns - Xns. .  Otherwise, if the cable is routed to the ECL-NIM converter, Correct time difference = DeltaT +5ns - Xns.

8c. Time for the ADCs: The cable from the patch panel to the ADC is 10ns long.  Correct time difference = DeltaT + Yns - 10ns - Xns.

9. The TDC requires a minimum of 45ns between the start and the stop.  Furthermore, the high resolution range is from the 45ns to 145ns.  The prompt peak in the timing spectrum should be within this range. 

10. The ADC requires a minimum of 25ns between the ADC gate leading edge and the signal leading edge for full intergration.

11. Changing the TDC start:  As seen in the level zero trigger schematic, the start for the TOF TDC's is routed to the Fastbus CAT module ICA Stop input via a 90ns cable.  The width of this cable is fixed, but the length can be changed.  It is necessary that the requirement in step 9 is meet.  Therefore, a single cable, to avoid an unnecessary jitter in the start, of the desired timing needs to be routed.

12. Changing the ADC gate:  The ADC gate is routed through a gate generator located in the bottom NIM bin in the rack to the right of the Fastbus.  The gate generator is in slot #11 and is the third module in the gate generator.  Trace the ADC gate cable from the ADC gate input on the CAT module to this gate generator as a double check. The gate generator is being used to delay the ADC gate.  The width and delay of the ADC gate can be adjusted at this gate generator.

13. Once the changes have been made, replace all signal and timing cable back to their nominal positions and make sure the inputs to the CAT module are properly terminated.