Some highlights of BRAHMS construction progress in September. Note that not all activities are covered.

• The counting house has been installed on the prepared site and the final inside preparation work is completing. Only remaining work before occupancy is installation of A/C power feeds, stairs and fire-protection. Work is in progress on air conditioning, experimental tray and power distribution for the F.E.hut.
• Contracts for mechanical and electric work for the magnet water system has been awarded. Construction is scheduled for completion by mid December.
• The Mid-rapidity platform has undergone mechanical safety reviews and loading with equipment can soon begin. The front forward platform assembly has been started; The track for it has been installed on the IR floor. Engineering design for the back platform has started.
• Work has been resumed on the D1 assembly. It is expected to be ready for mapping by early November. Power supplies for D2 and D5 have been installed on the mezzanine; AC and DC power has been connected.
• The production of the C1 vessel is ongoing in central shops.
• The drift chamber electronics will use the ASD8 chip and design on the cards has started. The first detector planes will be tested using L2735DC cards as well as some cards with the ADS8 chip made available on loan. (Krakow).
• The UVT radiators pieces for the Beam-Beam counter PMTs has been polished; assembly of the modules is about to start.
• The prototype TPC receiver board has undergone extensive testing. Transfers to the board are made from the Rosebud VME module controlled by a MVE2305 PowerPC processor. Data are pedestal subtracted, pedestal compressed and send to a FIFO on the board. The data are read via VME to the processor. Continuos testing has been done overnight. Only a few test remains before work will start on integration of the present board with the TPC readout board, as well as designing production version of the board.
• The final TPC readout board has not yet been received from STAR. They are investigating instabilities in operating the fiber link at 60 MHz, the design goal. The boards work with very low error rates at 50MHz transmission rates. The event readout time is governed by this transfer rate, thus an important issue.
• The DAQ development is proceeding with developments for and extensive testing of readout of multiple fastbus crates. Detailed plans for network communications and transfers for the daq vme processors are being worked on.
• The Mock Data Challenge started in early September. Many problems with tools developed to control the flow of data and programs between external disks and HPSS, and the reconstruction farms has been found and corrected. There has been good communication with the RCF on these issues. The Brat reconstruction code has also been modified extensively during this month as result of analyzing many different simulation data sets.